1. Field of the Invention
The present invention relates to bus interfaces and more particularly to a bus management interface that drives I2C and a high-speed interconnect interchangeably.
2. Description of the Related Art
Many similarities exist between seemingly unrelated designs in consumer, industrial and telecommunication electronics. Examples of similarities include intelligent control, general-purpose circuits (e.g., LCD drivers, I/O ports, RAM) and application-oriented circuits. The Inter-Integrated Circuit (I2C) bus is a bi-directional two-wire serial bus designed to exploit these similarities.
I2C buses can connect a number of devices simultaneously to the same pair of bus wires. Normally, the device addresses on the I2C bus are predefined by hardwiring on the circuit boards. A limitation of the v bus is that it will only allow a single device (e.g., an expansion board) to respond to each even address between 00 and FF. All addresses are even because only the high-order seven bits of the address byte are used for the address. Bit 0 is used to indicate whether the operation is to be a read or a write. Therefore, there are a limited number of addresses that can be assigned to a device.
With complex servers such as the IBM x3750 (“Kong”), many control signals from the base planer, need to be routed up to the CPU riser card. The signals are connected to the riser card using a backplane connector (e.g., a TinMan connector), but in most cases large numbers of pins are taken by chipset (e.g., an Intel chipset) required signals. As a result, only a small number of spare pins on the backplane connector remain for use by system management like functions. In many cases, the remaining pins are used for I2C communication. Many I2C devices are interrupt-driven and therefore stand idle for long periods of time not being used.